The inventive concept relates to a semiconductor memory device, and, more particularly, to a memory device for supporting a command bus training (CBT) mode and a method of operating the same.
A mobile-oriented memory device, such as a low power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM), is typically used in mobile electronic devices, such as a smart phone, a tablet PC, and/or an ultra-book. As the capacity of a mobile operating system (OS) increases to support multitasking operations performed by a mobile electronic device, it may be desirable to provide mobile electronic devices having a low power consuming characteristic and high speed operating performance.
To increase the high speed operating performance of a memory device, a high speed clock signal may be provided to an interface between the memory device and a memory controller (or a central processing unit (CPU)). The memory device may process signals received from the memory controller in response to a clock signal received from the memory controller and may synchronize signals transmitted to the memory controller with the clock signal. To support a high data transmitting speed, a frequency of the clock signal provided from the memory controller may increase. Therefore, it may be important for the memory device to correctly receive a transmitted signal. Therefore, the memory device may adopt a bus training technique.